The present application relates to a back-end-of-the-line (BEOL) interconnect structure and a method of forming the same. More particularly, the present application relates to an interconnect structure containing an interconnect level that contains an interconnect dielectric material layer having a first electrically conductive via feature, an electrically conductive line feature, and a second electrically conductive via feature embedded in the interconnect dielectric material layer, wherein the first and second via features are self-aligned perpendicularly to, and along the direction of, the electrically conductive line feature.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring, i.e., interconnect, structures.
Within typical dual damascene interconnect structures, electrically conductive metal vias run perpendicular to the semiconductor substrate and electrically conductive metal lines run parallel to the semiconductor substrate. Typically, the electrically conductive metal vias are present beneath the electrically conductive metal lines and both features are embedded within an interconnect dielectric material layer.
For a conventional self-aligned via process with a trench first metal hard mask integration scheme used in providing dual damascene interconnect structures, the vias are self-aligned perpendicular to the line (i.e., trench) direction, but not self-aligned along the line (i.e., trench) direction. This may cause potential via and line shorting problems. Also, an uncontrolled via chamfer may increase the risk of via to metal shorting, which, in turn, may result in poor electrical yield and low reliability.